1. Field of the Invention
The present invention relates to a thin film transistor, and more specifically, relates to a thin film transistor suitably used as a switching element for selectively switching a pixel electrode for an active matrix liquid crystal display apparatus.
2. Description of the Related Art
FIG. 43 is a plan view of a first conventional thin film transistor (hereinafter, referred to as a TFT) used for an active matrix liquid crystal apparatus, and FIG. 44 is a sectional view of the TFT taken along the line X44--X44 of FIG. 43. Referring to FIGS. 43 and 44, the first conventional TFT includes a gate electrode 1, a gate insulating film 8, a semiconductor layer 7 made of amorphous silicon, an etching stopper layer 6, ohmic contact layers 4 and 5 made of a phosphorus-doped semiconductor, and source and drain electrodes 2 and 3. All of these layers are formed in this order on an insulating substrate 9. The TFT having the above structure is called an inverted staggered type transistor.
FIG. 45 is a plan view of a second conventional TFT, and FIG. 46 is a sectional view of the TFT taken along the line X46--X46 of FIG. 45. The second conventional TFT is also an inverted staggered type transistor though it does not include an etching stopper layer as in the first conventional TFT.
FIG. 47 is a plan view of a third conventional TFT, and FIG. 48 is a sectional view of the TFT taken along the line X48--X48 of FIG. 47. Referring to FIGS. 47 and 48, the third conventional TFT includes source and drain electrodes 2 and 3, ohmic contact layers 4 and 5 made of a phosphorus-doped semiconductor, a semiconductor layer 7 made of amorphous silicon, a gate insulating film 8, and a gate electrode 1. All of these layers are formed in this order on an insulating substrate 9. The TFT having the above structure is called a staggered type transistor. Besides the transistors of the above-described types, those having structures called a inverted coplanar type as well as a coplanar type have also been realized. FIGS. 49 and 50 show TFTs of the inverted coplanar type and the coplanar type, respectively.
All of the above conventional TFTs include the ohmic contact layers 4 and 5 made of amorphous silicon doped with phosphorus (hereinafter, referred to as a-Si(n.sup.+)). They also have overlap portions 10, as shown in FIG. 44 for example, where part of the source electrode 2 and part of the drain electrode 3 are located right above part of the gate electrode 1 with the gate insulating film 8 therebetween.
A case where the source electrode 2 and the drain electrode 3 do not overlap the gate electrode 1 is shown by two-dot dash lines in FIGS. 43 and 44. In this case, gaps 12 are formed between the source electrode 2 and the gate electrode 1 and between the drain electrode 3 and the gate electrode 1 (hereinafter, the gaps 12 are referred to as non-overlap portions). The non-overlap portions 12 produce a resistance of an influential level which is connected in series with a resistance at the channel portion 42 when the TFT is activated. Hereinafter, the former resistance is referred to as a series resistance and the latter resistance is referred to as an ON resistance. The series resistance lowers the current-voltage characteristic of the TFT.
To prevent the production of the series resistance, the source electrode 2 and the drain electrode 3 should be formed so as to overlap the gate electrode 1. In practice, the patterns of electrodes are designed so that a sufficient margin for possible deviations of the patterns in a mask alignment of the photolithographic process. As a result, the areas of the overlap portions 10 become greater than the minimum requirement, and thus the size of the resultant TFT, that is, the area occupied by the TFT increases.
Meanwhile, when the source electrode 2 and the drain electrode 3 are formed to overlap the gate electrode 1 or the gate electrode 1 is formed to overlap the source electrode 2 and the drain electrode 3, a parasitic capacitance is produced between the source electrode 2 and the gate electrode 1 and between the drain electrode 3 and the gate electrode 1. Such a parasitic capacitance causes the generation of a direct-current component for the voltage applied to the pixel electrode. As a result, troubles such as after images and flickering occur, and thus the quality of the image deteriorates. In order to minimize the production of the parasitic capacitance, the areas of the overlap portions 10 should be minimized by, for example, reducing the sizes of the electrodes. However, according to the conventional techniques, since the margin for the deviation of the patterns is required as described above, it is difficult to reduce the areas of the overlap portions 10.
As shown in FIG. 43, a width W.sub.elect of the source electrode 2 and the drain electrode 3 is almost the same as a width W.sub.cont of the contact layers 4 and 5. The semiconductor layer 7 also has a width substantially the same as the width W.sub.cont of the contact layers 4 and 5, because the semiconductor layer 7 is etched together with the contact layers 4 and 5. A channel width W of the TFT is determined by the width W.sub.cont of the contact layers 4 and 5. When the width W.sub.elect of the source electrode 2 and the drain electrode 3 is made smaller than the width W.sub.cont of the contact layers 4 and 5, the effective channel width W.sub.rms becomes smaller. The effective channel width W.sub.rms is obtained by a current flowing through the TFT when the TFT is activated (hereinafter, referred to as an ON current). When the effective channel width W.sub.rms is smaller, the ON resistance of the TFT is greater, and thus the performance of the TFT is lowered. It is not practical, therefore, to make the width W.sub.elect of the source electrode 2 and the drain electrode 3 significantly smaller than the width W.sub.cont of the contact layers 4 and 5. Accordingly, it is not possible to reduce the areas of the overlap portions 10 by reducing the width W.sub.elect of the source electrode 2 and the drain electrode 3.
For the above reasons, the conventional TFTs are disadvantageous in that they cannot be reduced in size and their response characteristic is restrictive because of the production of the parasitic capacitance.